1. Technical Field of the Invention
This invention pertains to an input/output bus bridge and command queuing system. More particularly, it relates to a system for strictly ordering EOI commands relative to MMIO accesses while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses
2. Background Art
In a PowerPC computer system which is Common Hardware Reference Platform (CHRP) compliant, the external interrupt router receives interrupt commands from Bus Unit Controllers (BUCs) and responds with commands that include:
End of Interrupt (EOI)
INterrupt Return (INR)
Interrupt Reissue Request (IRR)
The function of the memory mapped I/O (MMIO) command is to send command information to, and retrieve status information from, Bus Unit Controllers and I/O devices. In some low performance devices, MMIO commands may be to transmit program data. The bridge unit responds to an MMIO command by determining the correct target (in the case of the preferred embodiment described hereafter, this is simplified to xe2x80x9con chipxe2x80x9d bus), then sending the command to that target. In the case of an MMIO Store command, data must be sent along with the command. In the case of an MMIO Load command, the response data (which arrives from the I/O device in response to the load command) is received by the bridge chip and placed on the system bus for receipt by the original requester.
The function of the Interrupt Return (INR) command is to inform the interrupting unit that its interrupt could not be processed due to a queue full condition. The interrupt routing unit in the bridge chip sends an INR command to an I/O device in response to receiving in interrupt command when the interrupt queues are full (the command returned may be different from the command received if the incoming interrupt has higher priority than one of the enqueued interrupts). Upon receiving an INR command, the interrupting unit (device or Bus Unit Controller) knows that its interrupt was not processed and that it is not allowed to resend the interrupt command until it receives an Interrupt Reissue Requests (IRR) command.
The function of the Interrupt Reissue Requests (IRR) command is to inform the interrupting unit(s) that the queue conditions in the interrupt routing unit (within the bridge chip) have changed and that it (the interrupting unit) should resend any previously returned (via INR command) interrupts. The interrupt routing unit in the bridge chip generates an IRR command anytime an interrupt is ended (anytime an EOI command is generated) and anytime the processing priority is changed (anytime the CPPR is modified by a processor). The IRR command is not targeted to a particular device, but is broadcast to all devices capable of generating an interrupt command.
The function of the End of Interrupt (EOI) command is to inform the interrupting unit that a previously sent interrupt has been received and acted upon by the processor. The interrupt routing unit sends an EOI command to an I/O device or Bus Unit Controller when a processor writes to one of the XIRR""s contained within the interrupt routing unit. The processor performs the write operation after processing for an interrupt is complete.
The routing of these response commands and the ordering of their delivery relative to other I/O commands has traditionally required a trade-off between performance and deadlock avoidance. Specifically, if the delivery of the EOI commands is strictly ordered with the delivery of Memory Mapped Input Output (MMIO) accesses, it is possible to eliminate many time consuming MMIO load operations from an operating system""s interrupt service routines and thereby significantly improve system performance.
Unfortunately, in a computer containing a hierarchical I/O bus structure implemented with multiple I/O Hub chips and Host Bridge Adapter chips, the strict ordering of all the interrupt response commands (EOI, INR, and IRRs) with MMIO accesses can result in deadlock conditions. Recovery from such deadlocks requires resetting some or all of the computer system hardware and the abandonment or restarting of software tasks in progress.
In prior art I/O Hub and Host Bridge Adapter chips, a mode bit is provided to allow software control of the ordering of all interrupt response commands relative to MMIO accesses. IBM AS/400 computer systems, for example, use these chips and choose strict ordering to improve system performance. Two consequences of this mode of operation are:
1. Software complexity required to detect and reset various deadlock situations.
2. System configurations which under utilize I/O bus bandwidth in an attempt to minimize the probability of deadlock by minimizing I/O traffic.
In another prior art system, the IBM RS/6000 computer system, the same I/O Hub and Host Bridge Adapter chips are used, in this case choosing not to order interrupt response commands (EOI, INR, and IRRs) relative to MMIO accesses. This allows higher bus utilization without the risk of deadlock, but results in reduced system performance resulting from additional MMIO load operations (to remote I/O BUCs) in the I/O interrupt service routines.
It is an object of the invention to provide an improved interrupt router and I/O command queuing mechanism.
It is a further object of the invention to provide an I/O hub chip which allows for ordering selected interrupt response commands to improve performance and priority delivery of other interrupt response commands for deadlock avoidance.
It is a further object of the invention to provide an interrupt router and I/O command queuing mechanism which allows for the elimination of many time consuming MMIO load operations from an operating system""s interrupt service routines without the risk of deadlock associated with ordering INR and IRR commands relative to MMIO accesses.
In accordance with system of the invention, an interrupt queuing system is provided. An interrupt routing unit is responsive to interrupt commands for generating first interrupt response commands and second interrupt response commands. A first command queue strictly orders the first interrupt response commands with memory mapped input output commands for loading to an input output bus. A second command queue loads the second interrupt response commands to the input output bus. Thus, the second interrupt response commands may be loaded to the input output bus irrespective of stalling of said first command queue.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.